1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of vertical power MISFET cells and method of manufacturing the same.
2. Description of the Related Art
Development of a semiconductor device has been proceeded to achieve both a higher breakdown voltage and a lower on-resistance in a power MOSFET at the same time.
For example, a semiconductor device called Super Junction structure has been proposed by Deboy, G., et al. in “A New Generation of High Voltage MOSFETs Breaks the Limit of Silicon”, IEDM Tech. Dig. (1998), P683-686. The device with such the structure causes a problem, however, because a large number of process steps are required for production and fine patterning of the size is difficult in the lateral direction or along the channel length.
In consideration of such the situation, the Applicant has proposed a semiconductor device including a power MOSFET and method of manufacturing the same, for example, in JP-A 2002-170955 (FIG. 7). The semiconductor device has a triple-layered pillar (such as NPN layers) formed to substantially serve the same role as the Super Junction structure to achieve both a lower on-resistance and a higher breakdown voltage at the same time. This semiconductor device can be produced, without invitation of a great increase in the number of process steps, in a smaller lateral size with a greatly lowered price.
The semiconductor device with the triple-layered pillar structure, however, causes a serge voltage when the power MOSFET transits the state from conductive to non-conductive. As a result, an avalanche current flows through drain-source. The maximum acceptable intensity of the avalanche current (avalanche withstand capability) is a very important subject matter in the power MOSFET. When the power MOSFET is kept non-conductive, a depletion layer is formed into a strip at a p-n junction between an n-type pillar layer and a p-type pillar layer, and a high electric field is placed across the depletion layer. If a serge voltage arises in such the condition, it causes local current crowding at the depletion layer. When the extent of the current crowding exceeds an acceptable value (avalanche withstand capability), it leads to device destruction at a high possibility.